International High Level Design Validation and Test Workshop, San Francisco, Vereinigte Staaten

IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high level descriptions, where high level refers to register&#8211;transfer, behavioral, and system level&#046; The goal of the workshop is to provide an informal forum, bringing together designers and test and verification researchers working in validating, debugging, synthesizing, and testing designs specified using high level descriptions, in an effort to address high level design, validation, and test issues concurrently&#046; <b>Keywords:</b> High Level Design Validation High Level Design Error Modeling High Level Test Bench Generation Testing Core Based Designs Hardware/Software Co&#8211;Testing Simulation&#8211;Based Verification Emulation and Prototyping Error Models and Verification Test Hardware/Software Co&#8211;Validation High Level DFT/Synthesis for Test High Level ATPG/Fault Simulation Validation of Microprocessors Design Error Debug & Diagnosis Formal Verification Methods On&#8211;Chip Software Testing High&#8211;Level Performance/Power Models