Run–Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse–grain FPFAs) appear to have more room for exploiting run–time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2003 aims to provide a forum for creative and productive interaction between all these disciplines. <b>Keywords:</b> Models & Architectures<br>Theoretical Models (RMesh, etc.), RTR Models and Systems, RTR Hardware Architectures, Optical Interconnect Models, Simulation and Prototyping, Bounds and Complexity Issues, Algorithms & Applications<br>Algorithmic Techniques<br>Mapping Parallel Algorithms, Distributed Systems & Networks, Fault Tolerance Issues, Wireless and Mobile Systems, Automotive Applications, etc., Technologies & Tools,<br>Configurable Systems–on–Chip<br>Energy Efficiency Issues, Devices and Circuits, Reconfiguration Techniques, High Level Design Methods, System support
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RAW
City
Santa FeNM
Country
United States
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