The IEEE European Test Workshop is a well–recognized forum for presenting and discussing hot topics, trends, emerging results, and practical applications in the area of electronic–based circuit and system testing.<br>TECHNICAL PROGRAM<br>The high–quality ETW′03 technical program during May 26–28 offers a keynote speech, paper presentations in two parallel tracks, embedded tutorials, poster presentations, and breakout discussions. The paper presentations are organized in a Research Track and an Applications Track. The Research Track addresses novel concepts and methodologies, while the Applications Track reports on industrial and/or academic experiences, developments, and case studies.<br>TUTORIALS<br>ETW′03 offers two full–day TTEP 2003 tutorials on May 25. * The tutorial on Testing (Embedded) Memories: New Fault Models, Tests, DfT, BIST, BISR, and Industrial Results, by Ad J. van de Goor (Delft University of Technology), discusses the more advanced topics in SRAM and DRAM testing. The tutorial addresses fault models, traditional memory tests as well as new march tests, testing two–port memories, optimal test strategies, DfT, BIST, and BISR techniques.<br>* The tutorial on Defect–Oriented Testing, by Peter Maxwell (Agilent Technologies) and Rob Aitken (Artisan Components), discusses effective defect–oriented test methods for CMOS ICs. The tutorial addresses defects and failure mechanisms, fault models, model validation, test generation, application of defect–oriented testing for improving product quality and lowering cost, and future trends in CMOS technologies and nanotechnologies.<br>SOCIAL EVENT<br>ETW′03 offers a Social Event in the beautiful surroundings of Maastricht. The friendly, inspiring atmosphere of ETW′03 allows plenty of opportunities to meet and interact with your colleagues in an informal setting. <b>Keywords:</b> Analog, Mixed–Signal, and RF Test, ATE Hardware and Software, ATPG and High–Level TPG, Debug and Diagnosis, Defect/Fault Tolerance and Reliability, Design Verification/Validation, Emerging Testability Standards, Failure Analysis, Defect and Fault Modeling, Fault Simulation, FPGA Test, High–Level DfT, IDDX Test, Low–Cost Testers, Memory and Processor Test, MEMS Testing, On–Line and Off–Line BIST, Scan–Based Techniques and Boundary Scan, Self–Repair Methodologies, Signal Integrity Test, System Test, Test of Embedded Cores and System–on–Chip, Test of MCMs and Boards, Test Resource Partitioning and Embedded Test, Test Synthesis and Synthesis for Testability, Thermal Testing, Yield Analysis and Yield Enhancement
Abbrevation
ETW
City
Maastricht
Country
Netherlands
Deadline Paper
Start Date
End Date
Abstract