DVCon (formerly called HDLCon) is the premier conference on the usage of Hardware Description Languages (HDLs), and Hardware Verification Languages (HVLs) for the design and verification of electronic systems and integrated circuits. The focus of the conference is on specialized languages such as VHDL, Verilog, SystemVerilog, SystemC, SUPERLOG, e and VERA, as well as general purpose languages such as C, and C++. Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of Electronic Design Automation (EDA) tools. <b>Keywords:</b> Experiences with top–down or bottom–up system–level design or verification, Experiences with System–on–Chip design, Designing and/or verifying FPGAs with embedded processors, Using multiple HDLs and/or HVLs in a design cycle, Techniques for directed test, random test, or other verification methods, Synthesizing high–level languages such as SystemC, SystemVerilog or C++, Experiences with hardware/software co–design, Experiences with mixed–signal simulation, Verification techniques that really work (and what did not work), Successful methods for reducing the time–to–market with electronic engineering projects, Any topic involving the use of an HDL or HVL
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DVCon
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San Jose
Country
United States
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