The CODES–ISSS Conference is the merger of two major international symposia on hardware/software codesign and system synthesis. <b>Keywords:</b> High–level, architectural and system–level synthesis, Specification and modeling, design representation, synthesis, partitioning, estimation, design space exploration, codesign for reliable systems. Codesign methodologies, test and debug strategies, interaction between architecture and software design, design space exploration beyond traditional, hw/sw boundary, theory and algorithms. System level models and semantics, timing, power, formal properties, heterogeneous systems and components Compilers, memory management, virtual machines, scheduling, concurrent software for SoCs, distributed/resource aware OS, OS and middleware support for application specific processors Heterogeneous multiprocessors, reconfigurable platforms, memory management support, communication, protocols, network–on–chip Network processors, media processors, app–specific HW accelerators, reconfigurables, low power embedded processors, bio/fluidic processors Low power, power–aware, testable, reliable, verifiable systems, performance modeling, validation and cosimulation, security issues System design, processor design, software, tools, case studies, trends, emerging technologies, experience maintaining benchmark suites, representation, interchange format, tools, copyrights, maintenance, reference implementations, and metrics. Hardware/software codesign Specification languages Embedded systems software Embedded systems architecture Application–specific processor architectures and synthesis Synthesis, modeling, and analysis Industrial practices and benchmark suites
Abbrevation
CODES-ISSS
City
Newport Beach
Country
United States
Deadline Paper
Start Date
End Date
Abstract