Timing Issues in the Specification and Synthesis of Digital Systems, Austin, Vereinigte Staaten

The eleventh in the TAU series, the TAU 2004 workshop aims to explore the temporal aspects of digital system design&#046; <b>Keywords:</b> Analysis and verification, Custom design analysis, Design and synthesis, Interconnect and clock tree synthesis, False paths problem, Timing&#8211;driven synthesis and re&#8211;synthesis, Optimal latch placement, Optimizing with composite cost functions, Formal theories and methods, Statistical variations and models, Wave pipelining, High performance architectures, Transistor&#8211;level timing, Timing issues in low power design, Systems on a chip, Delay models, Adjacent line switching and coupling, Performance evaluation, Incremental analysis, Clocking, synchronization and skew, Process variations, Asynchronous systems, Sensitivity analysis, Specification and abstraction, Special circuit families, System&#8211;level timing, Novel clocking schemes, Clock domains, static/dynamic logic Circuit&#8211;level timing