Design Conference, Santa Clara, Vereinigte Staaten

Abbrevation

DesignCon

Link

http://www.designcon.com

City

Santa Clara

Country

United States

Deadline Paper

2004-08-27

Start Date

2005-01-31

End Date

2005-02-03

Abstract

DesignCon is the premier annual Silicon Valley event for the electronic design automation (EDA) and semiconductor industry. The event features more than 90 technical sessions covering cutting–edge product case studies, design methodologies, and new product technologies, including nanotechnology. The technical exhibition consists of more than 130 leading EDA tool providers, semiconductor manufacturers, system–design houses, and Intellectual Property (IP) providers. In addition, the Reference Design Village in the exhibit area provides hands–on demonstrations of reference design kits described by related presentations in the technical sessions. This format of tightly coupled technical presentations and exhibits provides a unique and stimulating setting for design engineers to learn from each other. DesignCon is the first major EDA and system–on–chip (SoC) event each year, well positioned for new product announcements and company launches. The technical sessions, technical exhibiton, product demos, and Reference Design Village provide a platform for practicing engineers to interact with their peers in a manner conducive to finding solution to their most challenging design problems. DesignCon addresses the needs of electronic design engineers and allied professionals with a need to stay on top of current developments in design–engineering theory, technique, and application strategies. Keywords: Functional Verification/Validation Acceleration techniques, Application–specific processor design verification, Assertion–based verification, Asynchronous co–design, Debugging, Formal verification, Functional coverage, Hardware/software co–verification, Mixed–signal, RF, Partitioning, Prototyping Low–Power System Architecture Clocking, Implementation efficiency, Hardware vs. software, Leakage management, Low–power instruction sets, Multivoltage systems Advanced System Design (including embedded software & analog, RF, packaging) Cost efficiency, Data management & consistency, Design methodologies & management, Case studies, Distributed teams, Outsourcing, Hierarchical design, High–level design languages, IP cores, Nanotechnology, Platform–based design, Reconfigurable design, Reusability, System simulation and validation (inc. human interface, physical channels), System partitioning Physical Design (on–chip) Crosstalk, Interconnect, Leakage, Measurement, Mixed–signal, RF design, Modeling & simulation, Signal integrity, Timing closure, Physical timing closure, RT level Test & Debug Automatic test pattern generation, Design–for–test, Fault modeling, Self test & self repair, System redundancy, Test coverage, Testing gigabit I/O High–Speed, High–Performance System Design 10–40 Gbps design, Bus architecture physical design, Chip & system co–design, Design impacts of board materials, EMI effects, High data–throughput on copper, Interconnect, Cables & connectors, IC packaging, PCB, Via hole, Jitter, Measurement, Mixed–signal, RF design, Modeling & simulation, Open, scalable architectures, Optical designs, parallel optical modules, SerDes design techniques, Signal conditioning, Signal integrity, Crosstalk, Single–ended vs. differential I/O, Standards, Power distribution modeling, Power supply integrity Automotive System Design Challenges Wireless Design Challenges