The System Level Interconnect Prediction (SLIP) Workshop focuses on the modeling and prediction of usable properties of optimized interconnect systems. Both theory and applications of interconnect prediction techniques are highlighted.<br>Applications of SLIP techniques to architectural and micro–architectural exploration, physical design, and interconnect technology planning will be emphasized. In addition to the presentation of state–of–the–art papers in this field, the workshop has a tutorial component presented by leading researchers to encourage dialogue between the architecture, physical design, and interconnect technology communities. <b>Keywords:</b> Statistical properties of complex interconnect systems Architectural and micro–architectural effects on interconnect systems A priori, on–line, or a posteriori estimation of interconnect design parameters (wire length, area, and power) Applications of interconnect parameter estimations in architecture and CAD<br>Interconnect technology prediction for long–term industry roadmap projections<br>Interconnect technology planning and yield estimation for multilevel interconnect design<br>Techniques and calibrations for ″Rentian″ and ″non–Rentian″ interconnect estimation<br>Interconnect planning flows for specific target technologies (ASIC/SoC, FPGA, System–in–package, 3–D integration, molecular/nanoelectronics)<br>Design flows for low power and high performance objectives
Abbrevation
SLIP
City
Paris
Country
France
Deadline Paper
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