SNUG Europe is the annual meeting of Synopsys users from around Europe and beyond. It is an open forum that provides Synopsys users the opportunity to exchange ideas, discuss problems and explore solutions. SNUG also gives users a chance to meet with Synopsys executives and application engineers. <b>Keywords:</b> PHYSICAL DESIGN<br>There are tremendous challenges in getting from RTL or gate level netlist to tapeout, as designs get larger, faster, and more complex, with reduced power requirements and smaller feature sizes. User papers describing physical design insights, tool leverage, and successful strategies employed to meet these challenges are greatly welcomed. Back end physical designers are invited to share tool knowledge, best practices, and experiences in getting chips taped out on the following topics: – Scripts and Makefiles – Physical Synthesis – Place and Route – Timing Closure – Floorplanning – Clock Tree Synthesis – Routing – Signal Integrity – Power Planning – Physical Verification – Extraction – Low Power Design – Hierarchical Design<br>FUNCTIONAL VERIFICATION<br>As chips move to 10M gates and beyond, correct function depends on complex interaction of multiple subsystems. These designs incorporate embedded processors, complex busses, and IP. Today′s SoC designs require sophisticated verification methodologies to ensure working silicon. Tell us about your challenges on the topics below, and the role Synopsys tools have played: – Assertion Based – Formal Techniques – Verifying with Embedded IP – Speeding up Simulation – Mixed Signal Verification – HW/SW co–verification – Constrained, random verification techniques<br>SYNTHESIS<br>Synthesis continues to be the foundation for IC implementation. As IC designs get larger, faster, and more complex, it is increasingly important that results are optimal for physical design, test, and power in a highly productive and reliable process. Please share your experiences using the latest Synopsys technology to increase Synthesis productivity and meet todays design challenges including: – Compile strategies for best Area/Timing/Runtime – Scripts and Makefiles – Use of compute farms – Design Coding Styles – Datapath design – Integrating IP – Low Power Design – Testable Designs<br>TEST<br>Manufacturing test becomes more and more challenging as the sizes of chips increases and submicron physical defects require more advanced testing. Add to that the common requirement of keeping the cost of test under control and you are looking at new and innovating methodologies and tools. Tell us about your test challenges on the topics below, and how you have used Synopsys test tools to help solve your problems. – Design–for–Test – BIST Techniques – ATPG<br>FPGA<br>As the capability of FPGAs has grown into the multi–million equivalent ASIC gates, the designs that can be realized in FPGAs has grown apace. When the skyrocketing NRE and mask costs for ASICs are factored into the financial equation more and more people are using FPGAs either to prototype their design, to ship low volume products, or to ship the first products before the ASICs are shipped. Tell us about your challenges on the following topics and how you used Synopsys and vendor tools to help solve your problems. – ASIC Prototyping – High–end FPGA Methodology – Partitioning – Physical Design<br>TRANSISTOR DESIGN<br>Solutions in the areas of transistor level dynamic and static analysis are a critical part of tapeout, from design entry, to digital and mixed signal design. Designers are invited to share their experiences and flows on the challenging aspect of deep sub–micron transistor level design for IC and SOC: – Digital Transistor Verification – Analog Design – Mixed Signal – Static Timing Analysis – Design Entry<br>SYSTEM LEVEL DESIGN<br>System Level Design becomes a necessity for multi–processor SoC designs. As most of the functionality is actually in the software, the verification of software and hardware at the transaction–level allows SoC design teams to do more verification, much earlier in the design cycle, hence reducing the risk for costly chip re–spins. Tell us about your experiences with Synopsys system level solutions: – Transaction–Level modeling – Architecture exploration – SW verification with platform models – Algorithm design – Communication standards compliance verification
Abbrevation
SNUG
City
München
Country
Germany
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