International Test Synthesis Workshop, Santa Barbara, Vereinigte Staaten

Abbrevation

ITSW

Link

http://www.tttc-itsw.org/

City

Santa Barbara

Country

United States

Deadline Paper

2004-01-09

Start Date

2004-04-04

End Date

2004-04-07

Abstract

Design–for–Test continues to be a challenge with shrinking time–to–market windows, shrinking device geometries and increasing transistor densities. International Test Synthesis Workshop (ITSW) is a premier forum designed to share and exchange ideas, issues and best practices on the implementation of Design–for–Test (DFT) features in today′s complex ICs and System–on–a–Chip (SOC) designs. Keywords: Register Transfer Level DFT High–Level/Behavioral Test Synthesis System–on–a–Chip (SOC) DFT Memory and Logic BIST Test Synthesis for Debug and Diagnosis DFT for Mixed–Signal Circuits Test Synthesis for Reconfigurable Logic Test Scheduling and Test Resource Partitioning Power and Noise–Aware Test Non–scan and Partial Scan DFT Reducing the Cost of Test DFT Design Rule Checking DFT for At–Speed Test Synthesis for Testability Tester–on–a–Chip Board and System Test