Workshop on RTL and High Level Tesing, Osaka, Japan

The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing&#046; <b>Keywords:</b> Functional fault modeling<br>RTL ATPG<br>RTL DFT<br>RTL BIST<br>Relationship between RTL and gate level testing<br>High level approaches for testing / verification<br>SoC Testing