International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures, Palm Springs, Vereinigte Staaten

The NANOARCH workshop will investigate novel defect and fault tolerance architectures suitable for highly unreliable nanotechnologies&#046; The workshop will be a forum for presenting theoretical, simulation and case studies on new defect models, defect and fault tolerance architectures, reliability models and experimental reliability evaluation and validation frameworks related to defect and fault tolerant nanoscale architectures and computer aided simulation and design tools for these emerging nanotechnologies&#046; <b>Keywords:</b> Failure modes in emerging nanoscale device technologies including molecular electronics, quantum electronics, single electron transistors, carbon nanotubes and carbon nanowires Defect and fault models for emerging nanoscale device technologies Circuit, Logic and System level Testing methodologies for Nanoscale Architectures Yield models, yield analysis and yield enhancement in nanoscale technologies&#046; Device, Circuit, and System level Defect Tolerant Nanoscale Architectures Device, Circuit, and System level Fault Tolerant Nanoscale Architectures Emerging computational models for Nanotechnologies that consider reliability Novel Nanoscale Architectures that consider testing and reliability Dynamic reconfiguration in nanoscale architectures CAD for defect and fault&#8211;tolerant nanoscale systems