Abbrevation
NATW
City
Essex JunctionVT
Country
United States
Deadline Paper
Start Date
End Date
Abstract

The IEEE North Atlantic Test Workshop provides a forum for discussions on the latest issues relating to high quality, economical, and efficient testing methodologies and designs&#046; The 15th workshop will feature &#8242;&#8242;Testing in the high frequency world&#8242;&#8242;&#046; <b>Keywords:</b> Analog/Mixed Circuit Testing, Automatic Test Generation, Built&#8211;In Self&#8211;Test (BIST), Board Level Testing, Defect Oriented Testing, Delay/Performance Testing, Design for Testability, Design Verification/Validation, Diagnosis and Debug, Embedded Core Testing, Fault Modeling/Simulation, IDDQ Testing, Multi&#8211;Chip Module Testing, Memory Testing, MEMS Testing, Online Testing, System&#8211;on&#8211;Chip (SOC) Test, System Testing, Test Economics, Test Quality/System Reliability, Test Resource Partitioning, Test Synthesis