Following the traditions set up by its predecessors, MTDT06 will include all aspects of memory design, process technologies and testability related topics, such as memory circuit designs, cell structures, fabrication processes, design architectures and related testing and verification methods for SRAM, DRAM, Flash memory, EPROM, EEPROM, embedded memories, logic–enhanced and FIFO memories, 3–D memories, content addressable memories, etc. This year, the theme is on “Enabling Technologies for Memory Reliability and Yield,” covering all aspects of technical issues related to the theme. <b>Keywords:</b> Next–generation memory device<br>Memory testing<br>Next–generation memory process<br>Memory built–in self–test<br>DRAM cell design<br>Memory diagnosis & repair<br>Flash cell design<br>Cell Characterization<br>Cache memory design<br>Failure analysis<br>Multi–port SRAM design<br>Fault modeling<br>High–speed memory design<br>Yield analysis<br>Low–power memory design<br>Reliability analysis<br>Fault–tolerant architecture<br>Memory for space application<br>Memory compiler<br>Verification methodology<br>
Abbrevation
MTDT
City
Taipei
Country
Taiwan
Deadline Paper
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