Current defect tolerance, fault–tolerance and manufacturing test techniques are designed under the assumption that a system under test is composed largely of correctly functioning units. However, this assumption is severely tested in emerging nanoelectronics such as molecular electronics, quantum electronics, single electron transistors and carbon nanotubes and nanowires. In these nanoelectronics, self–assembly based fabrication results in failures rates an order of magnitude higher than in traditional CMOS. Consequently, defect and fault tolerance –at the physical, circuit and most importantly at the system level– is an enabling technology for building reliable nanoelectronic systems. NANOARCH will investigate novel defect and fault tolerance architectures targeting these highly unreliable nanoelectronics. The workshop will be a forum for presenting theoretical, simulation and case studies on new defect models, defect and fault tolerance architectures, associated experimental reliability evaluation and validation frameworks and computer aided simulation and design tools for these emerging nanoelectronics. <b>Keywords:</b> Defect tolerant nanoelectronic architectures at device, circuit, and system level<br>Fault tolerant nanoelectronic architectures at the device, circuit, and system level<br>Emerging computational paradigms for nanoelectronics<br>Modeling and simulation of novel nanoelectronic architectures and concepts Implementing micro–architectural concepts using nanoarchitectural building blocks<br>Dynamic reconfiguration in nanoelectronic architectures<br>Defect and fault models in emerging nanoelectronic device technologies<br>Manufacture testing methodologies for nanoelectronic architectures<br>Yield models, yield analysis and yield enhancement in nanoelectronics<br>CAD targeting defect and fault–tolerant nanoelectronic architectures<br>
Abbrevation
NANOARCH
City
Boston
Country
United States
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