The higher level of manufacturing susceptibility and field reliability in today’s SoC require enhanced detection, diagnosis and yield optimization solutions. These solutions necessitate incorporating on–chip infrastructure IP blocks, in addition to the functionality of the SoC. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This workshop analyzes this key trend and gives the chance to describe a range of infrastructure IP for today′s System–on–Chip (SoC) designs. This includes infrastructure IP for test, diagnosis, timing measurement, debugging, test, repair, and fault tolerance. <b>Keywords:</b> Embedded diagnosis IP<br>Design for Manufacturability<br>Built–in Repair Analysis and Built–in Self–Repair<br>Yield enhancement IP<br>Built–in monitors and embedded measurement functions<br>Embedded Test solutions (BIST)<br>On–line error detection and correction blocks<br>Transient error protection hardware<br>Process monitoring IP<br>Silicon debug infrastructure<br>
Abbrevation
I-IP
City
Berkeley
Country
United States
Deadline Paper
Start Date
End Date
Abstract