The Second Workshop on System Effects of Logic Soft Errors, Urbana, Vereinigte Staaten

Soft error in logic is an emerging concern for advanced silicon technologies&#046; SELSE 2 is intended to bring together a diverse group of participants from academia and industry to explore this problem from the device technology to systems behavior, simulation, and system level solutions&#046; This will be a forum to discuss your most current research and opinions on the topic&#046; We are interested in soliciting papers which cover the system level effects of logic SER from all perspectives&#046; Papers addressing both future and current technologies are requested&#046; Papers addressing error management in future technologies (including revolutionary nanotechnologies) will also be considered&#046; Illustrative case studies as well as future scenarios are solicited&#046; <b>Keywords:</b> What are the &#8243;new&#8243; mitigation techniques?<br>What is the overhead of soft error mitigation techniques?<br>Can soft error mitigation techniques successfully handle other types of errors?<br>How does one decide what mitigation technique is preferred?<br>How is system level derating predicted and measured?<br>What is the state of the art in system derating prediction?<br>Would it be useful to develop standard terms and metrics?<br>Can we develop a technology roadmap for SER?<br>