Abbrevation
IWLS
City
Vail
Country
United States
Deadline Paper
Start Date
End Date
Abstract

The International Workshop on Logic and Synthesis provides an international forum for promoting research and exchanging ideas about all aspects of integrated circuit and system synthesis,optimization, and verification&#046; The workshop encourages early dissemination of ideas and results&#046; Accepted papers are distributed only to IWLS participants&#046; Note, that due to the delayed schedule of DAC this year, papers submitted to DAC 2006 are also eligible for submission as regular papers&#046; Topics of interest include architectures and compilation, synthesis and optimization, power and timing analysis, design validation and verification, and design experiences, all applied at system description levels ranging from transistors to hardware&#8211;software interfaces&#046; Implementation might be in synchronous or asynchronous CMOS, or any emerging technology&#046; Submissions on modeling,analysis and tools targeting emerging technologies and platforms are particularly encouraged&#046; Authors may submit complete papers for their proposed presentation&#046; These must be no longer than 8 pages, double column, and in a 10&#8211;point font&#046; We also encourage submissions of extended abstracts in the early stages of research that highlight important new problems, perhaps without providing complete solutions&#046; Only electronic submissions will be accepted: submit at http://www&#046;iwls&#046;org&#046; For questions, contact IWLS pcchair@sigda&#046;org&#046; For travel grants, apply to ACM/SIGDA’s travel grant program at http://www&#046;sigda&#046;org/travelgrants&#046;html&#046; The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities to further stimulate interaction among participants&#046; For the first time, the workshop includes a programming challenge sponsored by IEEE CEDA for students&#046; The challenge is to implement one or more logic optimization algorithms on the industrial EDA database OpenAccess and to use the OA Gear infrastructure&#046; A jury will select significant contributions which are awarded with travel grants and one cash prize&#046; For more information, see http://www&#046;iwls&#046;org/challenge/ <b>Keywords:</b>