1st Workshop on Verification and Debugging, SeattleWA, Vereinigte Staaten

Knowing that a design violates its specification is only the first step towards a correct system&#046; The violation may be caused by a fault in the design, but also by an error in the specification or in the environment constraints&#046; A designer needs to understand the violation and to locate and correct the fault that causes it&#046; Industrial experience shows that fault localization and rectification take much more time, effort, and expense than fault detection&#046; Also, debugging often takes place late in the design cycle, which makes it a high&#8211;risk activity that may, if not done quickly and correctly, delay the release of a product&#046; The workshop addresses the technologies and methodologies that need to be employed after verification has detected the presence of a bug&#046; It aims to combine the efforts of the computer&#8211;aided verification and software engineering communities, attracting work in the areas of algorithms, tools, and methodologies for failure analysis&#046; We welcome submissions addressing debugging of software, circuit designs, or combinations of the two&#046; <b>Keywords:</b> explanation and simplification of error traces,<br>fault localization,<br>rectification of the design, the specification, or the environment description,<br>test case generation for debugging,<br>debugging techniques,<br>methodologies that facilitate debugging,<br>overviews that provide a novel view of the state of the art and stimulate discussion and further research, and empirical studies on debugging&#046;<br>