Abbrevation
STS
City
Chiba
Country
Japan
Deadline Paper
Start Date
End Date
Abstract

Semiconductor Equipment and Materials International (SEMI) is soliciting papers from authors around the world for the SEMI Technology Symposium 2006&#046; <b>Keywords:</b> < Device Technology ><br>Advanced Logic device<br>Memory Device<br>Sub&#8211;Micron CMOS transistor technology<br>Low Power Device<br>SOI Device<br>Analog Device<br>Device Modeling<br>Device Physics<br>< FEOL Process Technology&#12539;Material technology><br>Advanced Gate Insulator Technology<br>Metal Gate Electrode<br>Channel Formation: Epi&#65292;SiGe<br>USJ&#65292;Flash/Laser Annealing<br>Stress control technology&#65292;Strained Si and Device Characteristics<br>Other FEOL topics<br>Manufacturing Science<br>Improvement in efficiency of process Development and Spread of New Technology, and any other activities at Fab<br>&#8211; Yield Improvement<br>&#8211; Mass Scrap Restraint<br>&#8211; WIP Reduction<br>&#8211; SCM<br>&#8211; Improvement of OEE<br>&#8211; Saving Energy<br>&#8211; Cut Materials<br>&#8211; Zero&#8211;emission<br>&#8211; e&#8211;manufacturing<br>&#8211; 300mmPRIME<br>&#8211; 450mm manufacturing technology<br>Session/ Lithography<br>Excimer Steppers/Scanners<br>Immersion Lithography<br>Image Evaluation Technology<br>Aberration<br>Overlay<br>Focusing<br>Resolution Enhancement Technology<br>Photoresist<br>Light Source Development<br>NGL&#8211;Next Generation Lithography Tool: EB/EUV/NIL etc&#046;<br>Metrology<br>Lithography Simulation Technology<br>Session / DFM & Mask<br>DFM Technology<br>Design and Process Integration<br>OPC, PPC, RET Mask Data Processing<br>ORC, Process Modeling, Mask Printability Simulation<br>PSM and CPL<br>EUV Masks<br>Metrology<br>Defect Inspection/Repair<br>Cleaning/ Pellicle/ Haze Control<br>Quality Assurance<br>Process Control<br>Session/ Multilevel Interconnection<br>Low&#8211;k Film Technology<br>Advanced Metallization Technology (Cu, Al, Ag)<br>Advanced CMP Technology<br>Cu Electroplating<br>Atomic Layer Deposition<br>Damascene Technology<br>Interconnect Integration<br>Plug Formation Technology<br>Reliability of Interconnection<br>3D package<br>Session/ Etching<br>Low&#8211;k or Organic Film Etching<br>Damascene Fabrication Etching<br>Process Damage in Damascene Fabrication<br>Resist Remove Technique in Damascene Etching<br>Low&#8211;k or Organic Film Etching System<br>STI Etching<br>Gate Shrink Etching<br>Plasma Tolerance of ArF Photoresist Pattern<br>Damage Control<br>Other topics related to Etching<br>Session/ Packaging Technology/Packaging Materials<br>SiP Structure<br>CMOS/CCD Sensor Module<br>Low Cost Flip Chip Technology<br>Passive Components Embedded High Performance Substrate Technology<br>Module Packaging Technology<br>Assembly Technology in Ultra High Speed<br>Environmental Assembly Technology (Lead free, Eco&#8211;design)<br>Packaging Pieces & Materials<br>Packaging Process Technology<br>Assembly Equipment<br>Chip Stacking/3D Packaging<br>Packaging System Design<br>TAB/COF Technology<br>Packaging Design & Simulation<br>Wafer Level<br>MEMS Packaging<br>IC Tag<br>Low&#8211;k Interconnection Technology<br>Silicon Inter Poser<br>High Thermal Technology<br>EMI<br>LED/LASER Packaging<br>Wireless Interconnect<br>