Semiconductor Equipment and Materials International (SEMI) is soliciting papers from authors around the world for the SEMI Technology Symposium 2006. <b>Keywords:</b> < Device Technology ><br>Advanced Logic device<br>Memory Device<br>Sub–Micron CMOS transistor technology<br>Low Power Device<br>SOI Device<br>Analog Device<br>Device Modeling<br>Device Physics<br>< FEOL Process Technology・Material technology><br>Advanced Gate Insulator Technology<br>Metal Gate Electrode<br>Channel Formation: Epi,SiGe<br>USJ,Flash/Laser Annealing<br>Stress control technology,Strained Si and Device Characteristics<br>Other FEOL topics<br>Manufacturing Science<br>Improvement in efficiency of process Development and Spread of New Technology, and any other activities at Fab<br>– Yield Improvement<br>– Mass Scrap Restraint<br>– WIP Reduction<br>– SCM<br>– Improvement of OEE<br>– Saving Energy<br>– Cut Materials<br>– Zero–emission<br>– e–manufacturing<br>– 300mmPRIME<br>– 450mm manufacturing technology<br>Session/ Lithography<br>Excimer Steppers/Scanners<br>Immersion Lithography<br>Image Evaluation Technology<br>Aberration<br>Overlay<br>Focusing<br>Resolution Enhancement Technology<br>Photoresist<br>Light Source Development<br>NGL–Next Generation Lithography Tool: EB/EUV/NIL etc.<br>Metrology<br>Lithography Simulation Technology<br>Session / DFM & Mask<br>DFM Technology<br>Design and Process Integration<br>OPC, PPC, RET Mask Data Processing<br>ORC, Process Modeling, Mask Printability Simulation<br>PSM and CPL<br>EUV Masks<br>Metrology<br>Defect Inspection/Repair<br>Cleaning/ Pellicle/ Haze Control<br>Quality Assurance<br>Process Control<br>Session/ Multilevel Interconnection<br>Low–k Film Technology<br>Advanced Metallization Technology (Cu, Al, Ag)<br>Advanced CMP Technology<br>Cu Electroplating<br>Atomic Layer Deposition<br>Damascene Technology<br>Interconnect Integration<br>Plug Formation Technology<br>Reliability of Interconnection<br>3D package<br>Session/ Etching<br>Low–k or Organic Film Etching<br>Damascene Fabrication Etching<br>Process Damage in Damascene Fabrication<br>Resist Remove Technique in Damascene Etching<br>Low–k or Organic Film Etching System<br>STI Etching<br>Gate Shrink Etching<br>Plasma Tolerance of ArF Photoresist Pattern<br>Damage Control<br>Other topics related to Etching<br>Session/ Packaging Technology/Packaging Materials<br>SiP Structure<br>CMOS/CCD Sensor Module<br>Low Cost Flip Chip Technology<br>Passive Components Embedded High Performance Substrate Technology<br>Module Packaging Technology<br>Assembly Technology in Ultra High Speed<br>Environmental Assembly Technology (Lead free, Eco–design)<br>Packaging Pieces & Materials<br>Packaging Process Technology<br>Assembly Equipment<br>Chip Stacking/3D Packaging<br>Packaging System Design<br>TAB/COF Technology<br>Packaging Design & Simulation<br>Wafer Level<br>MEMS Packaging<br>IC Tag<br>Low–k Interconnection Technology<br>Silicon Inter Poser<br>High Thermal Technology<br>EMI<br>LED/LASER Packaging<br>Wireless Interconnect<br>
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City
Chiba
Country
Japan
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