The International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Vereinigte Staaten

Abbrevation

ERSA

Link

http://www.scism.lsbu.ac.uk/ERA/ersa06/ersa06.htm

City

Las Vegas

Country

United States

Deadline Paper

2006-02-20

Start Date

2006-06-26

End Date

2006-06-29

Abstract

The world is changing. The advances in microelectronics are changing the technology. One die can contain several billion transistors. This makes it possible, if not inevitable, to map into one die several processor cores. Also, the microelectronics market is changing. There is estimation that in the near future, in 2010, about 90% of applications are embedded systems, most of these are mobile, wireless consumer appliances that must be small in size, with very low power consumption and with high performance. This will emerge changes in the design concepts of microelectronic devices, the design concepts of application–specific processors, as well as general–purpose processors. Many companies and researchers believe that the challenge for future is to use reconfigurablilty and parallelism, introducing configurable multiprocessing on a single die. The reconfiguring is migrating from the circuit level to the level of algorithms, while hundreds, if not thousands, simple processor–cores are replacing complex processors on a single die. Configurable parallel processing has many advantages. First, it replaces time–consuming digital design by programming of multiprocessors reducing, thus, the design cost and time, and, makes the design reprogrammable. Second, algorithms are mapped directly onto configurable space of simple processors achieving the efficiency of Application–Specific Integrated Circuits (ASICs). Third, the multiprocessor concept facilitates the building of energy efficient systems using dynamic shutdown of unused processors. And last, the performance is scalable and depends on the algorithmic design, on the number of processors involved and not on the clock frequency of electrical circuits. The international conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) was founded in 2001 and, since then, has been held each year in Las Vegas. ERSA conference solicits papers from all aspects of reconfigurable computing, including classical programmable logic, as well as configurable multiprogramming related papers. The topics of interests include theory, architecture, algorithms, design systems and applications that demonstrate the benefits of reconfigurable computing. Keywords: Theory of Massively Parallelel Computing Theoretical models of computing in space and time Theoretical approaches of new computational aspects, including biologically inspired approaches Adaptive computing Mapping algorithms into hardware and synthesis of regular arrays Parallelization and space–time partitioning of algorithms System architectures using configurable computing platform Newly developed algorithms for efficient implementation on reconfigurable systems Software, CAD and Operating Systems CAD, specification, partitioning and verification Hardware compilation, hardware/software codesign, developing correct circuits High and low–level languages and compilers, design environments Operating systems and run–time reconfiguring IP–based and object oriented models and mapping methods Adaptive Hardware Architectures Adaptive and dynamically reconfigurable systems Reconfigurable processor architectures Complex systems using reconfigurable processors Application–tailored reconfigurable Systems–on–Chip Energy efficient systems on reconfigurable computing platform Applications Wireless communication systems Mobile communication systems, videophone, software radio, global positioning systems etc. Multimedia and virtual reality Video imaging, teleconferencing, data compression, image databases, computational geometry and computer graphics etc. Automotive industry Vehicle guidance, lane and obstacle detection, object recognition, traffic systems, navigation of robots etc. Security systems Object recognition and tracking, cryptology, Internet and security etc. Classical image and signal processing Digital filters, edge and line detection, morphological operators, motion and stereo estimation, discrete transformations, linear algebra, radar systems, object recognition etc.