Abbrevation
IWDTF
City
Kanagawa
Country
Japan
Deadline Paper
Start Date
End Date
Abstract

The 2006 International Workshop on &#8243;Dielectric Thin Films for Future ULSI Devices: Science and Technology&#8243; (IWDTF&#8211;06) will be held at Kawasaki City Industrial Promotion Hall in Kanagawa prefecture, Japan on November 8&#8211;10, 2006&#046; IWDTF started in 1999 (Tokyo) as a series of highly&#8211;successful annual domestic meeting on ultrathin silicon dioxide films&#046; In succession of the second international workshop (IWDTF&#8211;04) held in Tokyo, 2004, IWDTF&#8211;06 will focus on science and technology of gate insulators for MOS devices such as ultrathin SiO2, oxynitrides and alternate gate dielectric materials with higher dielectric constants, including ferroelectric thin films&#046; IWDTF&#8211;06 will further expand the scope to gate stack system around the dielectric thin films so as to include metal gate electrodes and mobility enhancement technologies in the channel layer&#046; This workshop will provide an opportunity for scientists and engineers to exchange information and ideas at the forefront of research on gate dielectrics and gate stacks for ULSI applications&#046; Selected topics of current interests will be reviewed by several invited talks&#046; Contributions of both experimental and theoretical studies that provide a deeper understanding of the properties and quality of gate dielectrics and interfaces are very welcome&#046; The workshop will consist of invited and contributed talks, and poster presentations&#046; <b>Keywords:</b> Ultrathin silicon dioxide, oxynitride and oxide&#8211;nitride composite dielectrics<br>High&#8211;k gate dielectrics<br>Metal gate electrodes<br>Mobility enhancement technology<br>Ferroelectric and high&#8211;k films for memory applications<br>Growth and related process of gate dielectric films<br>Electrical characterization of gate dielectrics<br>Gate dielectric wearout and reliability<br>Characterization and control of gate dielectric/Si interface<br>Surface preparation and cleaning issues for gate dielectrics<br>Dielectric reliability related to process integration<br>Theoretical approaches to gate dielectrics/Si structure<br>