The Metrology, Inspection, and Process Control for Microlithography conference at the SPIE Microlithography Symposium is the leading forum for the exchange of foundational information and discussion of novel concepts in patterning–related metrologies and inspection technologies. This conference welcomes original technical papers on metrology, inspection techniques, and process control. Metrology users and process control engineers require, and increasingly rely on, advanced process control methods utilizing effective analyses of the metrology and related data. The 2007 conference will expand its focus on methods and strategies for advanced process and tool control as well as fab–wide characterization, control, and prediction. Criteria for abstract peer review and rating will include contribution to scientific understanding, relevance and interest to the lithographic metrology and process control community, and lack of advertisements. Submitted papers must concentrate on the underlying technologies and methods, not on product marketing. <b>Keywords:</b> Metrology and Inspection Methodologies<br>optical, including full–field, near–field and scanned microscopy,<br>scatterometry, and interferometric techniques<br>particle beam (electron, ion), including scanned microscopy and elemental analysis<br>dimension metrology – critical dimensions, alignment and overlay<br>electrical probe and other device performance based metrology<br>applications to large–field/large–substrate/thin film heads/displays/MEMs<br>design rules, error budgeting, control accuracy, metrology error<br>diagnostics, culling, and feedback<br>metrology for lithography development, calibration and verification of print simulation<br>metrology for advanced resists and related patterning materials<br>design based metrology and inspection<br>new metrology requirements for emerging lithographic technologies<br>including immersion, imprint and EUV lithography.<br>Critical Dimension Metrologies<br>one dimensional and multi–dimensional (shape) metrology<br>edge profile<br>line–edge roughness<br>edge placement error.<br>Overlay, Registration, and Alignment Metrologies<br>photomasks, with predistortion, OPC, and phase shifting<br>mask precompensation related metrology on mask and wafer<br>novel overlay measurement techniques: high resolution optics, scatterometry, SEM, AFM<br>in–chip circuit overlay (inside die): SEM–based, novel optical methods.<br>Process Control, Characterization, and Yield Enhancement process optimization, monitoring, and quality assurance<br>feedback and feed forward efficient data analysis and visualization<br>issues and potential solutions for sub–65–nm design rule applications<br>metrology issues in 300–mm wafers<br>effective process control and impact on design performance limits.<br>Calibration and Accuracy<br>estimating total measurement error, including precision and accuracy<br>calibration techniques for metrology tools<br>line width, pitch standards, and reference materials<br>reference measurement systems, traceability and metrology comparisons<br>resolution<br>tool matching.<br>Defect Detection, Analysis and Control<br>contamination and defect control, detectability of patterning defects, environmental contamination<br>defect reduction, device performance and yield improvement, effective data use<br>systematic and design defect detection.<br>Limits of Metrology and Inspection Systems<br>scanning electron beam metrology<br>near–field optical microscopy<br>high–resolution imaging, AFM and scanning force microscopy<br>focused ion beam metrology (milling and imaging)<br>diffraction based metrology, scatterometry<br>novel techniques.<br>Measurement System Modeling and Simulation<br>physics of metrology processes, system–sample interaction<br>models of systems and samples; characterization and model parameters<br>predictive modeling; combining experimental and simulated data<br>novel data analysis methods, library–based image analysis, and algorithms sampling strategies.<br>Applications to ICs, Thin Film Heads, Systems–on–a–Chip, and Thin Film<br>Device Manufacturing<br>correlations between metrology, manufacturability, productivity, cost of ownership, and yield<br>novel application of statistical data analysis methods in manufacturing<br>process integration of image recording and transfer, etch, and deposition<br>metrology and related functional testing through self–test in systems–on–a–chip.<br>Mask Related Metrology<br>mask defect printability, particle, and defect detection and sizing<br>PSM and OPC mask metrology, design layout to wafer verification metrology.<br>
Abbrevation
MIPCML
City
San Jose
Country
United States
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