Formal Verification Methods for Hardware Design, Grenoble, Frankreich

Abbrevation

FVMHD

Link

http://www.ecsi.org

City

Grenoble

Country

France

Start Date

2006-06-27

End Date

2006-06-29

Abstract

The objective of the training is to give an overview of the use of formal verification methods for hardware design. After attending this training you will know: What is equivalence checking and how it is working. What is the meaning of assertions and how you use them to express design properties (the training presents the main assertions constructors using PSL but the concepts are independent of the language). How the verification by assertions is working. What is the correct by construction approach and why it can be an alternative. What are the advantages and disadvantages when using formal verification methods. How to introduce formal verification in the design flow. REGISTRATION FORM REGISTRATION FORM Please complete this form and fax it or mail it to: ECSI Office Parc Equation 2, Avenue de Vignate 38610 GIERES, France Ph: +33 476 63 49 34 Fax: +33 476 42 87 87 Email: office@ecsi.org http://www.ecsi.org Keywords: The role of formal methods in hardware design Validation of specifications, verification of a design step f Different techniques and tools: equivalence checking, model checking, theorem proving. Equivalence checking Representation of Booleans expressions f Proving equivalence with tools. Assertion–based design Principles of the technique (model checking) f Concepts for temporal property specification: LTL, CTL f The PSL standard f Practical use of PSL for verification by simulation, emulation, model checking. Theorem proving Different logics, same principle f Validation of high level functional specifications f Combining symbolic simulation and theorem proving to verify RTL. Rule–based design Expressing your design by rules f Guarantee the initial specification by refinement and proof: a protocol example f How to master the complexity by decomposition. Formal verification and legacy Re–use IPs ... and still have a formally verified system. Introduction of formal verification methods in the design flow.