IRPS offers its attendees technical sessions, tutorials, workshops, a year–in–review seminar and a poster session, all covering state–of–the–art developments in electronic and optoelectronic reliability. Attendees returning from IRPS will be better equipped to solve critical reliability problems and develop effective qualification procedures that affect their companies’ bottom line.<br><b>Keywords:</b> PRODUCT<br>Product Reliability and Burn–in – Product (Chip–level) Reliability Issues; New or Novel Failure Modes in Logic/Memory ICs, Burn–In Elimination Strategies, Wafer–Level Burn–In; Correlation Between Yield, Infant Mortality, Burn–In Fallout, Technology Model Predictions<br>Non–Volatile Memory – Unique Reliability Phenomena and Failure Mechanisms in Non–Volatile Memories; Reliability of Ferroelectric or Magnetic Memory Cells or Arrays<br>Qualification Strategies – New Techniques, Test Structures, and Product Vehicles for Technology or Chip Qualification; Best Practices to Reduce Cost and/or Time–to–Market; “Commercial” or “Extreme” Environments<br>Circuits – Comprehending Reliability in Designs and Circuits; Soft Error Upsets; Analog Circuit Reliability Issues;Simulation/Modeling Techniques<br>Assembly and Packaging – Package/Assembly Reliability, Stress Modeling, Cu and Low–K Issues, Chip Scale Integration, BGA and Flip Chip Assembly; Bump Reliability Issues<br>Failure Analysis – Evidence of New Failure Mechanisms and Failure Analysis Techniques, Case Histories<br>MEMS – Reliability of New Structures, Sensors, Actuators; Reliability Testing and Analysis of MEMS Systems; Design and Processing for Reliability<br>PROCESS<br>Device and Process – Reliability Driven Process Interactions; New Process–Related Reliability Issues. Including Si, and Non–Si based, OptoElectronics; MEMS, High Voltage devices and Nanotechnology<br>Transistor – New Hot Carrier Phenomena; NBTI; Transistor Scaling Issues; Impact of Alternative Gate Dielectrics; Effect of Materials’ Degradation; Silicon on Insulator (SOI) Reliability Issues; High Performance Transistor Reliability; Mobility Enhancement Techniques such as Strained Si. Metal Gate Integration and TFT Devices<br>Interconnects – Defect and Wearout Phenomena in Cu and Al Systems; Low–k/Oxide Inter/Intra–Level Reliability; Mechanical Stress Related Reliability Issues; Joule Heating Effects; Modeling Mechanical & Thermal Behavior; Fast/Slow Stress Correlations<br>Device Dielectrics – Oxide Breakdown Mechanisms; New or High–k Dielectric Materials Reliability; Processing Interactions;Wearout Models; Gate Dielectric Thickness Scaling; Stress Methodologies; Multiple Dielectric Technologies<br>ESD and Latch–Up – Novel Structures including SOI and Bipolar; Damage Interpretation; Circuit/Process Improvements; Scaling Issues, RF CMOS<br>Process Induced Damage – Reliability Degradation Associated with Damage; Early Non–Destructive In–Line Detection and Reliability Analysis<br>
Abbrevation
IRPS
Link
City
Phoenix
Country
United States
Deadline Paper
Start Date
End Date
Abstract