Abbrevation
SISPAD
City
Monterey
Country
United States
Deadline Paper
Start Date
End Date
Abstract

SISPAD provides an international forum for presenting leading edge research and development results in the area of process and device simulation&#046; SISPAD is under sponsorship of the IEEE Electron Devices Society (EDS)&#046; It is held annually, with the location of the conference circulating among Europe, Asia and the U&#046;S&#046; SISPAD is one of the longest running conferences devoted to semiconductor modeling&#046;<br>One of the unique strengths of SISPAD is its size&#046; SISPAD attracts approximately 200 participants from around the world&#046; The conference is the right size to allow for attendees to foster relationships and to relax among their peers&#046; SISPAD will have invited speakers who will present new ideas about device and process physics, demonstrate applications to leading edge technologies, and show new models for compact devices&#046;<br>Preceding the conference at the Monterey Plaza Hotel will be a companion workshop on Tuesday, Sept&#046; 5, 2006, &#8243;Gate Stack and Contact Engineering for sub&#8211;30nm FETs&#8243;, organized by R&#046; Dutton, Y&#046; Nishi, and K&#046; Saraswat of Stanford University&#046; This workshop is targeted at the discussion of critical issues facing scaled MOS technology with emphasis on the gate stack and contact technologies&#046; There are many challenges both in terms of technology and device design that need to be considered&#046; It is now generally accepted that alternative materials are needed to maintain good electrostatics and to reduce parasitic effects&#046; This workshop will explore these issues based on experimental and modeling work of leading experts in the field&#046;<br>We cordially invite you to attend SISPAD 2006 to learn more about state&#8211;of&#8211;the&#8211;art simulation models and applications, and to bask in the culture of the Monterey Peninsula&#046;<br><b>Keywords:</b> * All aspects of device simulation, including transport in nano&#8211;structures and structures using non&#8211;conventional materials, effects of strain on carrier transport, models of device scaling limits, quantum effects, reliability, fluctuations, and novel nano&#8211;scale devices such as QCA, SET, and molecular devices&#046;<br>* All aspects of process simulation, including both continuum and atomistic approaches, models for dopant activation and diffusion, oxidation, silicide growth, interface effects, and effects due to stress&#046;<br>* Interconnect modeling and algorithms including noise and parasitic effects&#046;<br>* Compact device modeling for circuit simulation, including high frequency and noise modeling&#046;<br>* Integration of circuit, device, process simulation with applications to performance modeling of circuits&#046;<br>* User interfaces and visualization&#046; * High performance computing, advanced numerical methods and algorithms, including gridding&#046;<br>* Simulations of new memory structures such as nanocrystal, phase change, MRAM, and devices such as microsensors, microactuators, optoelectronics devices, lasers, and flat panel displays&#046;<br>* Benchmarking, calibration, and verification of models and simulators&#046;