International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, Vereinigte Staaten

Abbrevation

TAU

Link

http://www.tauworkshop.com

City

Austin

Country

United States

Deadline Paper

2006-11-27

Start Date

2007-02-26

End Date

2007-02-27

Abstract

The TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas. Keywords: Analysis and verification Custom design analysis Integrated functional–temporal analysis Timing–driven synthesis and re–synthesis Circuit–level timing Formal theories and methods Statistical analysis techniques Transistor–level timing Timing issues in low power design Delay models and metrics Adjacent line switching and coupling Incremental analysis Clocking, synchronization, and skew Process variations Asynchronous systems Sensitivity analysis Special circuit families System–level timing Novel clocking schemes Clock domains, static/dynamic logic Layout impact on timing Uncertainty–based analysis Process & environmental variation models Power–delay tradeoffs Reliability impact on performance Incorporation of RETs in timing Circuit optimization Timing–driven layout optimization