VTS was organized in 1982 specifically to focus attention on newly developing test technology, particularly ATPG and Design for Test tools and methods. Since then, it has grown to include tutorials, panels, and innovative practices. VTS enjoys the participation of attendees from all over the world, and each year solicits new contributions in areas of current interest to the semiconductor test community.<br>Today, the VTS Program Committee annually invites original, unpublished paper submissions. Proposals regarding innovative practices and special sessions are also solicited. Innovative practice presentations highlight cutting–edge challenges faced by test practitioners, and innovative solutions employed to address them. Special sessions include, for example, panels, embedded tutorials, or hot topic presentations as they might emerge from year to year.<br><b>Keywords:</b> • Analog, M–S & RF Test<br>• Automatic Test Generation<br>• ATE Architecture & SW<br>• Board & System Test<br>• Built–In Self–Test (BIST)<br>• Current Based Test<br>• Defect Tolerance<br>• Delay & Performance Test<br>• Design for Testability (DFT)<br>• Design Verification/Validation<br>• Diagnosis and Debug<br>• Embedded System Test<br>• Embedded Test Methods<br>• Fault Modeling and Simulation<br>• Infrastructure IP<br>• MEMS Test<br>• Memory Test and Repair<br>• Microprocessor Test<br>• Multi–Chip Module Test<br>• Nanometer Technologies Test<br>• On–Line Test<br>• Power Issues in Test<br>• Self–Repair & Fault Tolerance<br>• System–on–Chip (SOC) Test<br>• System–in–Package Test<br>• Test Resource Partitioning<br>• Thermal Test<br>• Test Data Compression<br>• Test of High–Speed I/O<br>• Test Quality and Reliability<br>• Test Resource Partitioning<br>• Transients and Soft Errors<br>• Yield Analysis & Optimization<br>
Abbrevation
VTS
City
Berkeley
Country
United States
Deadline Paper
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End Date
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