This annual workshop provides a unique forum in the Middle East and Africa (MEA) region for researchers and practitioners in the areas of VLSI design, test and fault tolerance to come together to discuss new research ideas and present new research results. This event will provide the only VLSI Design &Test–specific meeting in the MEA region. <b>Keywords:</b> Design Methods and Tools:<br>· Nanotechnology architectures · MEMs · Quantum computing · Mixed–signal and RF design · Circuit simulation and timing analysis · IC physical design automation · Power analysis and low power design · Design verification · Logic synthesis · SOC/NOC/MPSOC design issues · Packaging · Design for manufacturability<br>Test Methods and Tools:<br>· DFT · Synthesis for testability · Test generation · Test simulation · iDDQ testing · Defect–based test · Fault modeling · Test issues in nanotechnology · BIST · Design for verification · Memory and FPGA test and repair · SOC/NOC/MPSOC test · Automatic test equipment · Analog and mixed–signal test · On–line testing · Test resource partitioning · Failure analysis · Fault tolerance · Process monitoring and control · Economics of test
Abbrevation
IDT
City
Dubai
Country
United Arab Emirates
Deadline Paper
Start Date
End Date
Abstract