Reconfigurable processing elements, whether used stand–alone or in conjunction with a general–purpose processor as part of an adaptive computer, have proven quite capable of providing high computational performance. By matching the processor structure to the needs of the current computation, this performance can be achieved at a much lower power consumption than with an equivalent general–purpose processor alone, and without incurring the tremendous mask and fabrication costs of a dedicated ASIC. Additional challenges, such as fault–tolerance and self–adaptation to changing environments, can also be met sucessfully using the technique of reconfiguration. It has thus been deemed the most important trend in computer and system architecture by the joint ITG/GI technical committee on the Architecture of Computing Systems (ARCS).<br>However, the granularity of the configuration process itself can vary between different solutions. It can occur just once, as in the case of a configurable processor whose instruction set is adapted to a specific problem domain, to occasionally, such as switching between different applications in a single system, up to dynamically, quickly altering the configuration even within a single application.<br>The focus of the very succesful past three Workshops on Dynamically Reconfigurable Systems (DRS) has traditionally just been the latter scenario. However, even the coarser–grained (re)configurations described above have been demonstrated as very useful in practice. Thus, for the first time, DRS is widening its scope to also address the entire spectrum of (re)configuration granularity. <b>Keywords:</b> Architectures of DRS and DRS components<br>Programming and processing models<br>Design and verification tools<br>Operating system support<br>Applications requiring (re)configurability
Abbrevation
DRS
City
Zürich
Country
Eswatini
Deadline Paper
Start Date
End Date
Abstract