The IEEE Latin–American Test Workshop provides an annual forum for test and fault tolerance professionals and technologists from Latin America and all over the world to present and discuss various aspects of system, board and component testing and fault–tolerance with design, manufacturing and field considerations in mind. The best papers presented at the 8th LATW will be invited to be re–submitted to the IEEE Design and Test of Computers and Journal of Integrated Circuits and Systems. <b>Keywords:</b> Analog Mixed Signal Test<br>E–Beam and Thermal Testing<br>On–Line Testing<br>Automatic Test Generation<br>Economics of Test<br>Process Control and Measurements<br>Built–In Self–Test<br>Fault Analysis and Diagnosis<br>Radiation Hardening Techniques<br>Defect–Based Test<br>Fault Modeling and Simulation<br>System–on–Chip Test<br>Dependability Estimation<br>Fault–Tolerance in HW/SW<br>Test Resource Partitioning<br>Design and Synthesis for Testability<br>Fault–Tolerant Architectures<br>Yield Optimization<br>Design Verification/Validation<br>Memory Test and Repair
Abbrevation
LATW
City
Cuzco
Country
Peru
Deadline Paper
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End Date
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