International Workshop on Power and Timing Modeling, Optimization and Simulation, 2007, Göteborg, Schweden

PATMOS 2007 is the seventeenth in a series of annual international workshops&#046; The PATMOS meeting has evolved into an important European event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design&#046; A peer review process is used to select the best of the submitted manuscripts for electronic and print publication&#046; <b>Keywords:</b> Low power design: high performance low power systems, ultra low power systems, special architectures&#046;<br>Modeling and synthesis: timing, power, low&#8211;voltage, interconnect, crosstalk&#046;<br>Timing design: clocking, synchronization, asynchronous and self timed systems, adiabatic switching&#046;<br>Optimization: low voltage low power logic families, logic parallelization, pipelining, fast low power arithmetic&#046;<br>Physical design: module generation, library optimization and characterization, area estimation&#046;<br>Physical test and characterization: low VT low voltage process, SOI, IDDQ, models and parameter extraction, experimental design for process control&#046;<br>Design methods and CAD tools: for low voltage low power design, high speed circuits&#046;<br>Trade&#8211;offs between devices, architectures and technologies, benchmark comparison&#046;