Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100–200 MHz range to 2–3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre–silicon verification approaches has been able to keep up with increasing chip complexity.<br>As ITSW moves to its new habitat in San Antonio, Texas, this year’s workshop will focus on post–silicon chip quality. ITSW 2007 will look at all aspects of testing in its natural habitat such as system bringup, system debug tools and architectures, re–use of pre–silicon DFT structures for post–silicon testing, hand–off of test IP, defect modeling, system test coverage metrics, SiP testing, system–level diagnostic methods, emerging standards for embedded testing, No–Fault Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. <b>Keywords:</b> * Register Transfer Level DFT<br>* High–Level/Behavioral Test Synthesis<br>* System–on–a–Chip (SOC) DFT<br>* Memory and Logic BIST<br>* Test Synthesis for Debug and Diagnosis<br>* DFT for Mixed–Signal Circuits<br>* Test Resource Partitioning<br>* Functional Verification<br>* Power and Noise–Aware Test<br>* DFT for At–Speed Test<br>* High–speed I/O test<br>* Reducing the Cost of Test<br>* Design for Manufacturing and Yield<br>* Board and System Test<br>* SER / Concurrent error detection<br>* Test Synthesis for Reconfigurable Logic
Abbrevation
ITSW
City
San Antonio
Country
United States
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