DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state–of–the–art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.<br><b>Keywords:</b> Yield Analysis and Modeling<br>Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.<br>Repair, Restructuring and Reconfiguration<br>Repairable logic, reconfiguration, repair; reconfigurable circuit design; DFT for on–line operation.<br>Testing Techniques<br>Built–in self–test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.<br>Error Detection, Correction, and Recovery<br>Self–testing and self–checking design; error–control coding; fault masking and avoidance; recovery schemes, space/time redundancy.<br>Defect and Fault Tolerance<br>Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults and errors.<br>Dependability Analysis and Validation<br>Fault injection techniques and environments; dependability characterization of IC and systems.<br>Emerging Technologies<br>DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self–assembly.<br>Design For Testability in IC Design<br>FPGA, SoC, NoC, ASIC, microprocessors.<br>Totally Fail–Safe Design for Critical Applications<br>Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine and space.<br>
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DFT
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Rome
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Italy
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