The 1st ACM/IEEE International Symposium on Networks on Chips (NOCS) is targeted as the premiere venue for architectural, circuits and design research into networks–on–chips. NOCS came about with a vision to establish a new research community that straddles traditional research area boundaries and encompasses research from diverse disciplines including computer architecture, CAD, general networking, VLSI design amongst others. <b>Keywords:</b> Network architecture (topology, routing, arbitration,...)<br>Power and energy issues in NoC<br>NoC case studies, application–specific NoC design<br>Timing, synchronous / asynchronous communication<br>NoC reliability issues<br>O/S support for NoC<br>Metrics and benchmarks for NoCs<br>NoC Network interface issues<br>Modeling, simulation, and synthesis of NoCs<br>Network–on–chip design methodologies<br>NoC Quality of Service<br>NoC support for CMP / MPSoC<br>NoC support for memory access<br>NoCs for FPGAs and structured ASICs<br>Programming models<br>Mapping of applications onto NoCs<br>Novel interconnect links / switches / routers<br>Signaling and circuit design for NoC links<br>Physical design of interconnect and NoC<br>NoC design tools<br>
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NoCs
City
PrincetonNJ
Country
United States
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