Field programmable gate arrays are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm impementation, systolic array, software accelerator or application specific architecture. However, the design complexity of FPGA′s and their role as buildling block in a high–performance computing system is subject to innovative research. Many diverse approaches exist, ranging from novel architectures, hardware–software codesign, evolvable hardware, evolutionary algorithms, reconfigurable computing, to the development of whole compiler, simulation and synthesis frameworks.<br>Since FPGA′s offer an inherently parallel computing paradigm, this mini–symposium of ParCo2007 is focusing on advances in this area.<br>Because of their versatility as an enabling component in parallel architectures, all areas of FPGA′s in parallel computing are addressed, in particular: methodology, performance analysis, architectures, algorithms and applications. Therefore you are cordially invited to participate or submit your contribution to this ParaFPGA symposium.<br><b>Keywords:</b> – parallel computing techniques with FPGA′s<br>– hardware/software co–design<br>– programming environments for FPGA′s<br>– interconnection networks<br>– FPGA arithmetic<br>– Multi–FPGA cores<br>– performance evaluation<br>– embedded FPGA platforms<br>– FPGA–based parallel applications<br>
Abbrevation
ParaFPGA
City
Juelich
Country
Germany
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