International Conference on Microelectronic Test Structures, Edinburgh, UK

Abbrevation

ICMTS

Link

http://www.see.ed.ac.uk/ICMTS/?http%3A%2F%2Foldeee_see_ed_ac_uk%2FICMTS%2F=

City

Edinburgh

Country

Deadline Paper

2007-11-01

Start Date

2008-03-24

End Date

2008-03-27

Abstract

The IEEE Electron Devices Society sponsors the 21st International Conference on Microelectronic Test Structures to be held in cooperation with the Scottish Microelectronic Center and the University of Edinburgh. The purpose is to bring together designers and users of test structures to discuss recent developments and future directions. The conference will be held at the University of Edinburgh on March 25–27, 2008. The conference will be preceded by a one–day Tutorial Short Course on Microelectronic Test Structures on March 24, 2008. There will be an equipment exhibition relating to test structure measurements. Original papers are solicited presenting new developments in test structures related to silicon, III–V compounds, nanotechnology, microelectronics and MEMS research. This includes their implementation, and applications as well as test structures aimed at the characterisation of new materials and devices. A Best Paper award will be presented by the Technical Program Committee. Keywords: Material and Process Characterisation Wafer start material evaluation, SiGe, strained silicon, Silicon–On–Insulator, Ge, GaAs, GaN and other compounds, homoepitaxial and heteroepitaxial layers. Resistivity, stress, contact resistance, dielectric, and interconnect measurements. Replicated Feature Metrology Level–to–Level registration, overlay, CD uniformity and control, non–electrical characterisation techniques, MOS effective gate length/width evaluation, mask and reticle process control. Manufacturing of Integrated Circuits Evaluation of individual and groups of integrated circuit, device and MEMS process steps and elements: transistors, diodes, device isolation, memory cells, and interconnect. Assessment of MMICs and RF components and products. Evaluation and optimisation of standard cell macros and other product circuits. Reliability and Product Failure Analysis Test structures for quality assurance, transistor, thin film, dielectric and interconnect reliability, thermal monitoring and analysis, accelerated wafer level tests, wafer level burn–in, failure identification, reliability prediction. Nanotechnology, Displays, MEMS, Sensors, and Emerging Devices Test structures to evaluate nanotechnology devices, displays, MEMS, physical/chemical sensors, image sensors and bio–sensors, amorphous silicon films and devices, micromachining, optoelectronic materials and devices. Device and Circuit Modelling Model parameter extraction, RF device modelling, de–embedding, pulsed measurements, high frequency measurement techniques and applications. Technology R&D, Yield Enhancement, Integration, and Production Process Control FEOL or BEOL evaluation, design rule determination, process uniformity and worst–case analysis, yield enhancement structures and methods, defect estimation structures and methods, yield modelling, evaluation of design–manufacturing interactions (Design for Yield), place and route methodology, Statistical Process Control. Large–scale, many–component test circuitry for technology assessment e.g. arrays, multiplexing techniques. Test Structure Measurement Utilisation Strategy Test equipment, probing and programmable testing for process diagnostics, optimizing test throughput, database and data analysis methods, statistical data analysis, expert systems and related techniques. Includes capacitance, voltage, current, resistance, optical, thermal etc measurements.