DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits.The focus of the conference is on the usage of specialized design and verification languages such as Veri l og, SystemVerilog,VHDL,PSL Syste mC,e, and VERA,as well as general p u rpose languages such as C and C++.Tools and methodologies include the use of te s t bench automation, hardware– assisted verification, h a rdware/ software co– verification, assertion–based and formal verification, and transaction– level system design and verification.<br>Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of Electronic Design Automation (EDA) tools.Presentations are highly technical in nature, and reflect real life experiences in using these languages and tools. <b>Keywords:</b> • Experience using ESL and TLM for system– level design and verification<br>• Experiences with System– on– Chip design<br>• Designing and/or verifying complex ASICs and FPGAs<br>• Using multiple HDLs and/or HVLs in a design cycle<br>• Techniques for generating constrained– random test,or other<br>automated stimulus generation methods<br>• Synthesizing transaction– level or abstract designs from high–level<br>languages such as SystemC,System Verilog or C++,to RTL<br>• Experiences with hardware/ software co–design and co– verification<br>• Experiences with mixed–signal simulation<br>• Verification techniques that really work (and what did not work)<br>• Verification process and resource management<br>• Verification methods that have achieved ze ro functional bugs in first silicon<br>• As s e rtion–based verification<br>• Coverage– driven verification<br>• Design and verification IP experiences, good and bad<br>• Measuring completeness and quality of verification: functional coverage,code coverage or other techniques<br>• Experience with formal technologies applied to verification, including the application of model checking and simulation together,or the use of dynamic formal verification tools<br>• Any topic involving the use of an HDL or HVL<br>
Abbrevation
DVCon
City
San Jose
Country
United States
Deadline Paper
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