Special Issue on Silicon Debugging and Diagnosis, Phoenix, Vereinigte Staaten

<P>Presilicon simulation, verification, and emulation cannot guarantee fault&#8211;free silicon products: Both design errors and manufacturing defects do happen&#046; Industry surveys show that up to 75% of all IC designs require one or more design respins&#046; Yield ramping is extremely important, especially for advanced process technology nodes&#046; We need to learn from early, prototype silicon in order to improve the design process, the manufacturing process, or both&#046; The good news when studying silicon is that we are looking at the “real thing”; it is inherently more accurate and faster than any simulation model used in the presilicon phase&#046; However, the bad news is that controllability and observability are difficult, and they get more difficult with every process technology node, requiring special design measures up front&#046;</P> <P> <B>Keywords:</B> </P> <UL> <LI>New methodologies, case studies, and surveys <LI>Chip&#8211;level debugging and diagnosis <LI>IP&#8211;core&#8211;level debugging and diagnosis <LI>Design debugging <LI>Diagnosis of manufacturing defects <LI>Standards on debugging <LI>DFT reuse for debugging <LI>Economics of debugging <LI>Electrical debugging and diagnosis methods <LI>Physical debugging and diagnosis methods </LI></UL>