IEEE/ACM SYMPOSIUM ON NANOSCALE ARCHITECTURES, San Jose, Vereinigte Staaten

Abbrevation

NANOARCH

Link

http://www.nanoarch.org/

City

San Jose

Country

United States

Deadline Paper

2007-08-06

Start Date

2007-10-21

End Date

2007-10-22

Abstract

The purpose of the NANOARCH symposium is to be a forum for the presentation and discussion of novel architectures and design methodologies by considering these issues in future nanoscale implementations. The symposium seeks to build on the successes of NANOARCH 2005 and NANOARCH 2006. NANOARCH is interested in novel architectures including massively parallel, biologically inspired as well as those that are defect and fault tolerant, case studies on defect, fault and yield models, experimental reliability evaluation, validation frameworks, computer aided simulation, and design tools and emerging computational models for nanoelectronics. The symposium topics of interest include. Keywords: <LI>Architectures for nanoelectronic digital and mixed–signal circuits and systems <LI>Computational paradigms and programming models for nanoscale architectures <LI>Modeling and simulation of nanoelectronic devices, circuits and system architecture <LI>Simulation of complex systems with nanoscale computing architectures <LI>Implementing microarchitecture concepts using nanoarchitecture building blocks <LI>Defect and fault tolerant nanoelectronic device, circuit, and system level architectures <LI>Manufacture testing of nanoelectronic architectures <LI>Computer aided design tools and methodologies for nanoelectronic architectures </LI>