2nd IEEE International Workshop on Design for Manufacturabilit and Yield, Santa Clara, Vereinigte Staaten

Abbrevation

DFM&Y

Link

http://vlsicad.ucsd.edu/DFMY2007/

City

Santa Clara

Country

United States

Deadline Paper

2007-08-31

Start Date

2007-10-25

End Date

2007-10-26

Abstract

Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aim at improving the manufacturing process and consequently its yield by enhancing communications across the design – manufacturing interface. A wide range of Design–for–Manufacturability (DFM) and Design–for–Yield (DFY) methodologies and tools are proposed today. Some of which are leveraged during the back–end design stages, and others have post design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM can dramatically impact the business performance of chip manufacturers. It can also significantly affect age–old chip design flows. Using a DFM solution is an investment and thus choosing the most cost effective one(s) requires trade–off analysis. The workshop analyzes this key trend and its challenges, and gives the opportunity to discuss a range of DFM and DFY solutions for today′s SoC designs. Keywords: Analog and mixed–signal DFM Test–based yield learning Statistical design Resolution enhancement technology Infrastructure IP Variability–aware design Built–in process monitors Repair analysis and reconfiguration Yield management DFM via adaptive design Optical proximity correction Critical area analysis<?xml:namespace prefix = o ns = ″urn:schemas–microsoft–com:office:office″ />