13th IEEE European Test Symposium, Verbania, Italien

Abbrevation

ETS

Link

http://www.ieee-ets.org/

City

Verbania

Country

Italy

Deadline Paper

2007-12-07

Start Date

2008-05-25

End Date

2008-05-29

Abstract

The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, practical applications, hot topics, and new trends in the area of electronic–based circuit and system testing. In 2008, ETS will take place in the nice town of Verbania, Piedmont, Lago Maggiore lakeside. ETS’08 is being organized by the Politecnico di Torino, and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society. Keywords: <TABLE style=″WIDTH: 732px; HEIGHT: 195px; TEXT–ALIGN: left″ cellSpacing=2 cellPadding=2 border=0> <TBODY> <TR> <TD style=″VERTICAL–ALIGN: top; WIDTH: 183px; FONT–STYLE: italic″>• Automatic Test Generation • Fault Modeling and Simulation • Current–Based Test • Power Issues in Test • Thermal Test • Delay and Performance Test • High–Speed IO/Interconnect Test • Signal Integrity Test • Nanometer Technologies Test • ATE Hardware and Software • Standards in Testing</TD> <TD style=″VERTICAL–ALIGN: top; WIDTH: 183px; FONT–STYLE: italic″>• Test(ability) Synthesis • Built–In Self Test (BIST) • Design for Test(ability) (DfT) • Test Data Compression • On–Line Test • Self–Repair Methodologies • Test of Reconfigurable Systems • Analog, Mixed–Signal, RF Test • Memory Test and Repair • Microprocessor Test • MEMS and Nanotechnology Test</TD> <TD style=″VERTICAL–ALIGN: top; WIDTH: 183px; FONT–STYLE: italic″>• Failure Analysis • Diagnosis and Debug • Design Verification and Validation • Test Quality and Reliability • Yield Analysis and Enhancement • Defect and Fault Tolerance • Board and System Test • (Embedded) System Test • High–Level DfT and TPG • System–in–Package (SiP) Test • System–on–Chip (SoC) Test</TD></TR></TBODY></TABLE>