9th European Workshop on Ultimate Integration of Silicon, Udine, Italien

Abbrevation

ULIS

Link

http://www.ulisconference.org/

City

Udine

Country

Italy

Deadline Paper

2008-01-18

Start Date

2008-03-12

End Date

2008-03-14

Abstract

The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains. Keywords: <UL> <LI>Nanometer scale devices: physics, technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.<?XML:NAMESPACE PREFIX = O /><O:P></O:P> <LI>CMOS scaling perspectives; device / circuit level performance evaluation; switches and memory scaling.<O:P></O:P> <LI>New channel materials for CMOS electronics: strained Si, strained SOI, SiGe, GOI, III–V and high mobility materials for MOSFET; carbon based electronics; carbon nanotubes; graphene based devices.<O:P></O:P> <LI>Thin gate dielectrics: first and second generation high–k materials for switches and memory.<O:P></O:P> <LI>Alternative transistor architectures including PDSOI, FDSOI, DGSOI, FinFETs, MuGFETs, vertical MOSFET, IMOS and tunnel FET structures. Benchmarking of new architectures w.r.t. bulk CMOS.<O:P></O:P> <LI>One dimensional and zero dimensional structures: nanowires, nanotubes, nanodots. Nanowire and nanotube based interconnects; nanocrystal based NVM memory cells.<O:P></O:P> <LI>Variability and fluctuation phenomena in electronic switches and memory devices. Single electron, few electron, discrete dopant and discrete charge effects in scaled electron devices.<O:P></O:P> <LI>Advanced physics based modeling and simulation of nanoscale switches and memory. First principle and ab–initio modeling of devices, materials and interfaces for CMOS. <O:P></O:P> <LI>Quasi ballistic, ballistic and quantum transport in nanoscale devices. Compact modeling of nanoscale devices. Modeling and management of thermal effects. Benchmarking of modeling approaches.<O:P></O:P> <LI>Process characterization through device parameter extraction, device and electrical characterization of nanometer scale technologies.<O:P></O:P> <LI>CMOS compatible molecular and quantum devices; non conventional nanodevices for sensors, actuators and bioelectronics. NanoCMOS to bio– and opto– interfaces.<O:P></O:P> </LI></UL>