<P>The 2008 International ESD Workshop (IEW) will focus on robust design strategies and ESD/EOS testing of state–of–the–art integrated circuits, advanced semiconductor system on chip (SOC) and system in package (SIP) applications.</P> <P> <B>Keywords:</B> Novel Design Concepts – New protection device and circuit concepts, high sensitivity & high speed circuit challenges, off–the–wall ideas<BR>Special Custom Design Approaches – High voltage application designs, protection design for analog circuits, BiCMOS and Bipolar protection, GaAs protection<BR>Technology Integration Issues – ESD sensitivity with technology transfers, qualification challenges for different fabs, unusual problems of process interaction with ESD, process monitor methods<BR>Failure Analysis – New techniques to detect ESD/EOS failures, correlation between HBM/MM/CDM/TLP with physical FA, unusual and strange failure modes Structures – Design of standard structures for It2, gate oxide and metal current density monitor; special VFTLP test structure design and analysis<BR>Simulation Tools – TCAD interpretation examples, device behavior under ESD like conditions, standard SPICE simulation techniques to verify ESD designs, ESD checking tool development<BR>Component Level ESD Testing – Tester to tester correlation, ESD tester artifacts, and test standards issues<BR>ESD Characterization – Failure debug procedures, correlation of TLP and HBM and correlation of vf–TLP and CDM<BR>System Level ESD Issues – On–Chip and Off–Chip IEC protection device techniques, cable discharge, transient latchup effects<BR>Immunity of ICs to EMI – Characterization methodologies, modeling, protection strategies<BR>Unresolved ESD Issues – Random and unrepeatable ESD failures, issues with ESD standards, ESD data statistics </P>
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IEW
City
Port D\'Albret
Country
France
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