The International Symposium on Networks–on–Chip (NOCS) provides a high quality forum for scientists and engineers to present their latest research findings in the area of NoC–based systems at all levels, from the physical on–chip link level through the network level, and ranging up to systems architecture and application software. <B>Keywords:</B> <UL type=DISC> <LI>Network architecture (topology, routing, arbitration,...) <LI>Power and energy issues in NoC <LI>NoC case studies, application specific NoC design <LI>Timing, synchronous /asynchronous communication <LI>NoC reliability issues <LI>O/S support for NoC <LI>Metrics and benchmarks for NoCs <LI>NoC Network interface issues <LI>Modeling, simulation, and synthesis of NoCs <LI>Network–on–chip design methodologies <LI>NoC Quality of Service <LI>NoC support for CMP / MPSoC <LI>NoC support for memory access <LI>NoCs for FPGAs and structured ASICs <LI>Programming models <LI>Mapping of applications onto NoCs <LI>Novel interconnect links / switches /routers <LI>Signaling and circuit design for NoC links <LI>Physical design of interconnect and NoC <LI>NoC design tools <LI>Debug & Test of NoC <LI>Floorplan aware NoC architecture optimisation </LI></UL>
Abbrevation
NoCs
City
Newcastle University
Country
UK
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