Abbrevation
IWDTF
City
Tokyo
Country
Japan
Deadline Paper
Start Date
End Date
Abstract

The 2008 International Workshop on “Dielectric Thin Films for Future ULSI Devices: Science and Technology” (IWDTF&#8211;08) will be held at Tokyo Institute of Technology, Meguro&#8211;ku, Tokyo, Japan, on November 5&#8211;7, 2008&#046; The IWDTF started in 1999, based on a domestic annual workshop on ultrathin silicon dioxide films&#046; In succession to the second (IWDTF&#8211;04, Tokyo) and the third (IWDTF&#8211;06, Kawasaki) workshops, the IWDTF&#8211;08 will focus on the science and technologies of gate dielectric films for MOS devices, such as ultrathin SiO<SUB>2</SUB>, SiON, high&#8211;k gate dielectrics, and ferroelectric films&#046; The topics on other technologies involved in the advanced gate stacks, which include metal gate electrodes and high&#8211;mobility channel materials, will also be discussed&#046; The IWDTF will provide a great opportunity for information exchange and discussions at forefront of the researches on future ULSI&#046; The papers on both experimental and theoretical studies, for the deep understanding of the properties of gate dielectric films and their interfaces, are welcomed&#046; The workshop will consist of invited and contributed talks, and poster presentations&#046; Selected topics of current interests will be reviewed by several invited talks&#046;<BR><B>Keywords:</B> <LI>Ultrathin silicon dioxide, oxynitride and oxide&#8211;nitride composite dielectrics <LI>High&#8211;k gate dielectrics <LI>Metal gate electrodes <LI>Mobility enhancement technology <LI>Ferroelectric and high&#8211;k films for memory applications <LI>Growth and related process of gate dielectric films <LI>Electrical characterization of gate dielectrics <LI>Gate dielectric wearout and reliability <LI>Characterization and control of gate dielectric/Si interface <LI>Surface preparation and cleaning issues for gate dielectrics <LI>Dielectric reliability related to process integration <LI>Theoretical approaches to gate dielectrics/Si structure </LI>