International Workshop on Power and Timing Modeling, Optimization and Simulation, 2008, Lisbon, Portugal

PATMOS 2008 is the eighteenth in a series of international workshops&#046; The PATMOS meeting has evolved into a leading scientific event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design&#046; PATMOS 2008 is organized by INESC&#8211;ID and the Technical University of Lisbon, in Lisbon, Portugal&#046;<b>Keywords:</b><br><p><b>Timing and Performance</b></p> <ul><li>Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction; </li><li>Statistical Timing Analysis, Design for Yield, Design for Manufacturability; </li><li>Special timing or performance related topics, e&#046;g&#046; crosstalk, synchronization, GALS, side&#8211;channel attacks&#046; </li></ul> <p><b>Power Dissipation</b></p> <ul><li>Design techniques for low power circuits and systems at all levels of abstraction; </li><li>Methods and tools for analysis, characterization, design and optimization of the power consumption; </li><li>Low power architectures and libraries; </li><li>Special power related topics, e&#046;g&#046; low voltage, leakage power, power grid, interconnect power, clock tree power, power aware test pattern generation, thermal effects&#046; </li></ul> <p><b>Design Experience and Case Studies</b></p> <ul><li>Examples, test cases, benchmarks or design studies which present innovative solutions for timing, performance or power consumption related design challenges&#046; </li></ul>