The IEEE VLSI Test Symposium, San Diego, Vereinigte Staaten

Abbrevation

VTS

Link

http://www.tttc-vts.org/public_html/new/2008/index.php

City

San Diego

Country

United States

Deadline Paper

2007-11-05

Start Date

2008-04-27

End Date

2008-05-01

Abstract

The VTS Program Committee invites original, unpublished paper submissions for VTS 2008. Paper submissions should be complete manuscripts, up to eight pages (inclusive of figures, tables, and bibliography) in a standard IEEE two–column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. Keywords: • Analog, M–S & RF Test • Automatic Test Generation • ATE Architecture & SW • Board & System Test • Built–In Self–Test (BIST) • Current Based Test • Defect Tolerance • Delay & Performance Test • Design for Testability (DFT) • Design Verification/ Validation • Diagnosis and Silicon Debug • Embedded System Test • Embedded Test Methods • Fault Modeling and Simulation • Infrastructure IP • MEMS Test • Memory Test and Repair • Microprocessor Test • Multi–Chip Module Test • Nanometer Technologies Test • On–Line Test • Power Issues in Test • Self–Repair & Fault Tolerance • System–on–Chip (SOC) Test • System–in–Package Test • Test Resource Partitioning • Thermal Test • Test Data Compression • Test of High–Speed I/O • Test Quality and Reliability • Test Resource Partitioning • Transients and Soft Errors • Yield Analysis & Optimization