International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, Vereinigte Staaten

Abbrevation

TAU Workshop

Link

http://www.tauworkshop.com/

City

Monterey

Country

United States

Deadline Paper

2007-11-26

Start Date

2008-02-25

End Date

2008-02-26

Abstract

The TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas. Keywords: <TABLE style=″WIDTH: 779px; HEIGHT: 292px; TEXT–ALIGN: left″ cellSpacing=2 cellPadding=2 border=0> <TBODY> <TR> <TD style=″VERTICAL–ALIGN: top; FONT–FAMILY: Tahoma″>Formal theories and methods System–level timing Transistor–level timing Circuit–level timing Sensitivity analysis Full custom design analysis Integrated functional–temporal analysis Incremental analysis Timing issues in low power design Power–delay trade–offs Adjacent line switching and coupling Delay models and metrics Layout impact on timing Timing–driven layout optimization</TD> <TD style=″VERTICAL–ALIGN: top″>Timing–driven synthesis and re–synthesis Circuit optimization Uncertainty–based analysis Incorporation of RETs in timing Reliability impact on performance Process & environmental variation models Statistical analysis technique Clocking, synchronization, and skew Clock domains, static/dynamic logic Novel clocking schemes Special circuit families Asynchronous systems </TD></TR></TBODY></TABLE>