<P>The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing WRTLT′08, the ninth workshop, will be held in conjunction with the 17th Asian Test Symposium (ATS′08) in Sapporo, Japan. </P> <P><B>Keywords:</B> (1) High level testing –– RTL/Behavior level testing, High level approaches for testing,<BR>RTL ATPG, RTL DFT, RTL BIST, Synthesis for testability, Relationship between RTL<BR>and gate level testing, Functional fault modeling, High level test bench generation<BR>(2) SoC testing –– Test scheduling, Core testing, Interconnect testing, NoC testing<BR>(3) Reliable SoC –– System level reliability, Self repair, Fault tolerant SoC<BR>(4) Micro processor testing<BR>(5) Design Verification<BR>(6) Gate level test related issues –– Low power testing, Test compression, ATPG, DFT,<BR>BIST</P>
Abbrevation
WRTLT
City
Sapporo
Country
Japan
Deadline Paper
Start Date
End Date
Abstract